1. Field
An embodiment of the present invention relates to integrated circuits, and more particularly, to reducing signal transmission delay using skewed gates.
2. Discussion of Related Art
With the scaling of semiconductor process technologies, threshold voltages of metal oxide semiconductor circuits are typically being reduced with reductions in supply voltages in order to maintain circuit performance. Lower transistor threshold voltages lead to significant increases in leakage current due to the exponential nature of sub-threshold conductance.
Increased leakage current can be a problem for all types of logic, but in particular, for domino and other dynamic logic. Domino logic is widely used in many high speed critical-paths in microprocessors, for example, due to its speed and area advantage over static complementary metal oxide semiconductor (CMOS) logic. Increases in leakage current cause severe noise problems for domino and other dynamic logic because of the use of precharge logic in such circuits.
One approach to addressing the higher leakage current that results from lower threshold voltages has been to use a dual threshold voltage technique. In a dual threshold voltage approach, certain devices on a particular integrated circuit are designed and fabricated to have a first, low threshold voltage, while other devices on the same integrated circuit are designed and fabricated to have a second, higher threshold voltage. In this manner, devices, such as devices in dynamic circuits that cannot tolerate the higher leakage current characteristic of lower threshold voltages can be selected to have higher threshold voltages.
Using this approach, in the sub-1 volt supply voltage region, the threshold voltages of devices used in domino logic are typically raised over that of static CMOS logic in order to provide an adequate noise margin. For this reason, the performance advantage of domino logic can degrade with technology advancement. In fact, at some point, the performance of domino logic falls below that of static CMOS logic as supply voltages continue to decrease. Further, semiconductor processing of such circuits is complicated by the need to provide transistors having multiple threshold voltage on the same integrated circuit die.
Another consequence of technology scaling is that interconnect delays are becoming a more important factor in terms of determining the performance of high speed integrated circuits such as microprocessors. For example, a larger and larger percentage of a processor clock cycle is now attributed to interconnect delay.
One approach to addressing this issue has been to insert repeaters, typically buffers or inverters, at various points along an interconnect. Interconnect delay is proportional to the square of the length of the interconnect wire. These repeaters are inserted to bring the interconnect delay back to a range where it is approximately linearly proportional to the length of the interconnect wire.
While this approach is helpful, there is still a need to further reduce interconnect delay as integrated circuit technologies continue to increase in speed.